Packaging methods and packaged devices
US9059107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2012 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Sep 12, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.