Packages for three-dimensional die stacks
US9059127B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2014 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Jan 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16747
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.