Extensible network-on-chip
US9064092B2 · kind B2 · utility
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9References
12Claims
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Key dates
| Filing date | Aug 10, 2012 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Jan 2, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises compute nodes arranged in an array; a torus topology network-on-chip interconnecting the compute nodes; and a network extension unit at each end of each row or column of the array, inserted in a network link between two compute nodes. The extension unit has a normal mode establishing the continuity of the network link between the two corresponding compute nodes, and an extension mode dividing the network link in two independent segments that are accessible from outside the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.