Semiconductor memory device and memory system including the same
US9064603B1 · kind B1 · utility
5Cited by
7References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 20, 2014 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Feb 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.