Patent · US Active

Trap rich layer formation techniques for semiconductor devices

US9064697B2 · kind B2 · utility

8Cited by

22References

22Claims

0Family size

Assignee

Silanna Semiconductor U.S.A., Inc. · US

Inventors

Anton Arriagada · San Diego, US
Michael A. Stuber · Carlsbad, US
Stuart B. Molin · Carlsbad, US

Key dates

Filing date	Aug 28, 2013
Grant date	Jun 23, 2015
Priority date	—
Expiry date	Aug 28, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/201
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.