Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors
US9064903B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2014 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Feb 5, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.