Patent · US Active

I/O cell ESD system

US9064938B2 · kind B2 · utility

3Cited by

5References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Melanie Etherton · Austin, US
Alexey Gilgur · Holon, IL
James W. Miller · Austin, US
Jonathan M. Phillippe · Austin, US
Robert S. Ruth · Austin, US

Key dates

Filing date	May 30, 2013
Grant date	Jun 23, 2015
Priority date	—
Expiry date	Oct 4, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/05554
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O cells. The ESD network includes ESD clamp cells and ESD trigger circuit cells wherein a portion of the network is located in the row. In some examples, the row includes an ESD trigger circuit cell with a portion in one subarea of one ESD subarea of one I/O cell and a second portion in a second ESD subarea of another I/O cell. Also described herein is a method for producing an integrated circuit layout with an ESD network.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.