Capacitor charging circuit with low sub-threshold transistor leakage current
US9065433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2013 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Dec 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K4/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A capacitor charging circuit has input, output and control nodes, first and second series connected primary FETs, and first and second leakage current reduction FETs. All of the FETs have their gates coupled to the control node. The first primary FET is coupled between the input and output nodes, and the second primary FET is coupled between the output node and a leakage current reduction node. The first leakage current reduction FET is coupled between a supply line and the leakage current reduction node, and the second leakage current reduction FET is coupled between the leakage current reduction node and ground. When a control signal at the control node is low, the first primary FET and the first leakage current reduction FET are conductive, and the second primary FET and the second leakage current reduction FET are non-conductive, which eliminates sub-threshold leakage current flowing through the second primary FET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.