Phase locked loop with self-calibration
US9065454B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2013 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.