Bad wordline/array detection in memory
US9065481B2 · kind B2 · utility
7Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2013 |
| Grant date | Jun 23, 2015 |
| Priority date | — |
| Expiry date | Jun 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.