Concurrent page table walker control for TLB miss handling
US9069690B2 · kind B2 · utility
6Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Mar 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.