System and method of distributed initiator-local reorder buffers
US9069912B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | Mar 31, 2012 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Nov 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4031
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in reorder buffers, some of which include storage to allow multiple simultaneously pending transactions. Transactions are transported by a packet-based transport protocol. The reorder buffering is done at packet level, within the transport topology. Reorder buffers are distributed physically throughout the floorplan of the chip, they have localized connectivity to initiators, and they operate in separate power and clock domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.