Memory circuitry with write assist
US9070431B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2013 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Oct 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory circuitry is provided with write assist circuitry for generating a lower power supply voltage during write operations. The write assist circuitry includes a plurality of series connected switches including a header switch and a footer switch. Header bias circuitry generates a header bias voltage and footer bias circuitry generates a footer bias voltage. The header bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. The footer bias voltage is an analog signal with a voltage level intermediate between the power supply voltage level and the ground voltage level. During write operation target bit cells to be written are supplied with the power via a current path through the header switch while these are respectively controlled by the header bias voltage and the footer bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.