Mismatch error reduction method and system for STT MRAM

US9070466B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Mihail Jefremow · Augsburg, DE
• Wolf Allers · Munich, DE
• Jan Otterstedt · Unterhaching, DE
• Christian Peters · Mountain View, US
• Thomas Kern · Munich, DE

Key dates

• Filing date: Sep 6, 2012
• Grant date: Jun 30, 2015
• Expiry date: Sep 9, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/1673
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.