Refresh architecture and algorithm for non-volatile memories
US9070473B2 · kind B2 · utility
14Cited by
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18Claims
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Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Feb 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/5678
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.