Adaptive standard cell architecture and layout techniques for low area digital SoC
US9070552B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2014 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | May 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A standard cell CMOS device includes a first power rail extending across the standard cell. The first power rail is connected to one of a first voltage or a second voltage less than the first voltage. The device further includes a second power rail extending across the standard cell. The second power rail is connected to an other one of the first voltage or the second voltage. The second power rail includes a metal x layer interconnect and a set of metal x−1 layer interconnects connected to the metal x layer interconnect. The device further includes a set of CMOS transistor devices between the first and second power rails and powered by the first and second power rails. The device further includes an x−1 layer interconnect extending under and orthogonal to the second power rail. The x−1 layer interconnect is coupled to the set of CMOS transistor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.