Pattern forming method and method of manufacturing semiconductor device
US9070559B2 · kind B2 · utility
0Cited by
6References
6Claims
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Key dates
| Filing date | Mar 4, 2014 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Mar 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.