Heterojunction bipolar transistors with reduced parasitic capacitance

US9070734B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Renata Camillo-Castillo · South Burlington, US
• Vibhor Jain · Williston, US
• Vikas K. Kaushal · South Burlington, US
• Marwan H. Khater · New York, US

Key dates

• Filing date: Oct 30, 2014
• Grant date: Jun 30, 2015
• Expiry date: Oct 30, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/138

Abstract

Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.