Semiconductor device
US9070736B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 2014 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Sep 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/112
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A p-type thin-layer along a side wall surface of a V-shaped groove reaching the bottom portion of a p-type isolation layer from the back surface of an n− semiconductor substrate, couples a p-type collector layer with the p-type isolation layer. A collector electrode contacts the surfaces of the p-type collector layer and the p-type thin-layer. The collector electrode is formed by laminating an Al—Si film, a barrier layer, a nickel-based metal film, and a gold-based metal film in sequence from the n− semiconductor substrate side. The Al—Si film contacting the surface of the p-type collector layer is in a range of 1.1 to 3.0 μm in thickness. The Al—Si film contacting the surface of the p-type thin-layer is in a range of 0.55 to 1.5 μm in thickness. A rise in leak current caused by aluminum spiking is eliminated or suppressed, and solder joining including tin is made easier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.