Successive approximation analog-to-digital converter with linearity error correction
US9071265B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Jun 30, 2015 |
| Priority date | — |
| Expiry date | Aug 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A SAR ADC includes capacitors, a comparator, and a SAR logic circuit. The capacitors include a first set of capacitors and an error-detection capacitor. The first set of capacitors generates a first set of voltage signals that are compared with a common-mode voltage signal (VCM) by the comparator during a first set of comparison cycles. The comparator generates a first set of control signals that is used by the SAR logic circuit to successively approximate the first set of voltage signals and generate a first set of bits. An error-detection capacitor generates an error-detection signal that is compared with the common-mode voltage signal VCM by the comparator to generate an error-detection control signal. The SAR logic circuit compensate for an error in the first set of bits based the logic state of the error-detection control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.