Array substrate and liquid crystal display device including the same
US9075269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/134309
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes a substrate; gate lines over the substrate along a first direction; data lines over the substrate along a second direction and crossing the gate lines to define pixel regions; a thin film transistor at each crossing portion of the gate and data lines; an insulating layer covering the thin film transistor and having a flat top surface; a common electrode on the insulating layer all over the substrate; a common line on the common electrode; a passivation layer on the common line; and a pixel electrode on the passivation layer in each pixel region and connected to the thin film transistor, the pixel electrode including electrode patterns, wherein the passivation layer has a step height at a top surface of the passivation layer due to the plurality of common lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.