Method of application memory preservation for dynamic calibration of memory interfaces
US9075543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2014 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for calibrating a memory interface circuit is described wherein prior to a calibration operation at least a portion of application information contained in a memory circuit is moved or copied to an alternate location to preserve that information. At the completion of the calibration operation, the information is restored to the same location of the memory circuit. Thus, the calibration operation can be performed from time to time during normal operation of a system containing the memory circuit. Non-limiting examples of calibration operations are described including operations where a capture clock for a memory read circuit is calibrated, and operations where CAS latency compensation is calibrated for a DDR memory interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.