Managing power consumption in a multi-core processor

US9075614B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Eric Fetzer · Longmont, US
• Reid James Riedlinger · Fort Collins, US
• Don Soltis · Windsor, US
• William J. Bowhill · Marlboro, US
• Satish Shrimali · Bengaluru, IN
• Krishnakanth V. Sistla · Beaverton, US
• Efraim Rotem · Haifa, IL
• Rakesh Kumar · Bengaluru, IN
• Vivek Garg · San Mateo, US
• Alon Naveh · Ramat HaSharon, IL
• Lokesh Sharma · Bengaluru, IN

Key dates

• Filing date: Mar 1, 2013
• Grant date: Jul 7, 2015
• Expiry date: Aug 19, 2033

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D30/50
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.