Patent · US Active

Method and apparatus for memory encryption with integrity check and protection against replay attacks

US9076019B2 · kind B2 · utility

7Cited by

0References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Shay Gueron · Haifa, IL
Uday Savagaonkar · Redmond, US
Francis X. McKeen · Portland, US
Carlos V. Rozas · Portland, US
David M. Durham · Beaverton, US
Jacob Doweck · Haifa, IL
Ofir Mulla · Netanya, IL
Ittai Anati · Ramat HaSharon, IL
Zvika Greenfield · Kfar Sava, IL
Moshe Maor · Kiryat Shmona, IL

Key dates

Filing date	Jun 29, 2011
Grant date	Jul 7, 2015
Priority date	—
Expiry date	Jun 29, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH04L9/3242
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a “time stamp” indicator associated with the cache line. The “time stamp indicator” is stored in a processor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.