Memory cells breakdown protection
US9076522B2 · kind B2 · utility
12Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Sep 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.