Electrostatic discharge (ESD) clamp circuit with high effective holding voltage

US9076656B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Melanie Etherton · Austin, US
• Alex P. Gerdemann · Austin, US
• James W. Miller · Austin, US
• Mohamed S. Moosa · Austin, US
• Robert S. Ruth · Austin, US
• Michael A. Stockinger · Austin, US

Key dates

• Filing date: May 2, 2013
• Grant date: Jul 7, 2015
• Expiry date: Aug 9, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/921

Abstract

Boosted Electrostatic Discharge (ESD) clamp circuit with high effective holding voltage. In some embodiments, an integrated circuit may include a trigger circuit operably coupled to a first voltage bus and to a reference bus; a diode including an anode terminal operably coupled to a second voltage bus, the second voltage bus distinct from the first voltage bus; a transistor including a gate operably coupled to an output terminal of the trigger circuit, a drain operably coupled to a cathode terminal of the diode, and a source operably coupled to the reference bus; and an input/output (I/O) cell operably coupled to the first voltage bus, the second voltage bus, and the reference bus.