Electronic system comprising stacked electronic devices comprising integrated-circuit chips
US9076749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2014 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Oct 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.