Patent · US Active

System and method of varying gate lengths of multiple cores

US9076775B2 · kind B2 · utility

0Cited by

6References

37Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Ming Cai · Hopewell Junction, US
Samit Sengupta · San Jose, US
Chock Hing Gan · Singapore, SG
PR Chidambaram · Richardson, US

Key dates

Filing date	Sep 4, 2013
Grant date	Jul 7, 2015
Priority date	—
Expiry date	Sep 4, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method includes forming a first poly-silicon gate of a first transistor, the first poly-silicon gate having a first length. The first transistor is located in a first core. The method also includes forming a second poly-silicon gate of a second transistor, the second poly-silicon gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.