Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage
US9076837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2012 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Jul 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly a lateral insulated gate bipolar junction transistor (LIGBT), and a method of making it are provided in this disclosure. The device includes a silicon-on-insulator (SOI) substrate having a drift region, two oppositely doped well regions in the drift region, two insulating structures over and embedded in the drift region and second well region, a gate structure, and a source region in the second well region over a third well region embedded in the second well region. The third well region is disposed between the gate structure and the second insulating structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.