Method of forming a low power dissipation regulator and structure therefor
US9077256B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2010 |
| Grant date | Jul 7, 2015 |
| Priority date | — |
| Expiry date | Oct 7, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method of forming a conditioning circuit includes configuring an output biasing network to provide a biasing voltage to an MOS transistor to enable the MOS transistor to operate in a saturated operating mode for input voltages that are less than a threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.