Patent · US Active

Architecture to allow efficient storage of data on NAND flash memory

US9081668B2 · kind B2 · utility

3Cited by
1References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 14, 2013
Grant dateJul 14, 2015
Priority date
Expiry dateSep 19, 2033

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02D10/00
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a pre-determined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.