Network communications processor architecture
US9081742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2010 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Oct 16, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/506
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described embodiments provide a system having a plurality of processor cores and common memory in direct communication with the cores. A source processing core communicates with a task destination core by generating a task message for the task destination core. The task source core transmits the task message directly to a receiving processing core adjacent to the task source core. If the receiving processing core is not the task destination core, the receiving processing core passes the task message unchanged to a processing core adjacent the receiving processing core. If the receiving processing core is the task destination core, the task destination core processes the message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.