Memory module for high-speed operations
US9082464B2 · kind B2 · utility
10Cited by
24References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Aug 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes a plurality of buses. A plurality of memory chips is mounted on a module board and is connected to a first node, a second node, and a plurality of third nodes of the plurality of buses. The first node, the second node, and the third nodes branch off to a first memory chip, a second memory chip, and the third memory chips, respectively. A length of the plurality of buses between the first and second nodes is longer than a length of the plurality of buses between adjacent nodes from among the second node and the third nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.