Row decoding circuit and memory
US9082486B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Jan 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A row decoding circuit and a memory are provided. The row decoding circuit is adapted for providing a word line operation voltage and a control-gate line operation voltage to a dual-bit split gate flash memory array, and includes a dummy row decoding unit, at least one row decoding unit and a driving voltage generating circuit. The dummy row decoding unit includes a first dummy control-gate line voltage output, a second dummy control-gate line voltage output and at least one dummy word line voltage output. The row decoding unit includes a first control-gate line voltage output, a second control-gate line voltage output and at least one word line voltage output. The driving voltage generating circuit is adapted for providing a third driving voltage to the first control-gate line voltage output and the second control-gate line voltage output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.