Read assist circuit for an SRAM, including a word line suppression circuit
US9082507B2 · kind B2 · utility
10Cited by
6References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2014 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | May 7, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving the array supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a first switch coupled in series and a second switch. The switches are responsive to a control signal. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.