Packaging methods and structures for semiconductor devices
US9082636B2 · kind B2 · utility
3Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2014 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Oct 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.