Inventor · Kaohsiung, TW

Bor-Ping Jang

42Patents
5h-index
30Co-inventors
69Inventor score

Filing activity: Jan 13, 1997 → Jul 27, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US8381965B2 Thermal compress bonding Electricity 23 Active
US8884431B2 Packaging methods and structures for semiconductor devices Electricity 22 Active
US5843831A Process independent alignment system Electricity 20 Expired
US9093337B2 Methods for controlling warpage in packaging Electricity 17 Active
US10157881B2 Methods for controlling warpage in packaging Electricity 6 Active
US9484226B2 Methods for controlling warpage in packaging Electricity 4 Active
US9768142B2 Mechanisms for forming bonding structures Electricity 4 Active
US8951037B2 Wafer-level underfill and over-molding Electricity 4 Active
US9659891B2 Semiconductor device having a boundary structure, a package on package structure, and a method of making Electricity 3 Active
US9082636B2 Packaging methods and structures for semiconductor devices Electricity 3 Active
US7005236B2 Maintaining photoresist planarity at hole edges Physics 2 Expired
US10020211B2 Wafer-level molding chase design Electricity 2 Active
US8616433B2 Forming low stress joints using thermal compress bonding Emerging Cross-Sectional Technologies 2 Active
US10510712B2 Methods for controlling warpage in packaging Electricity 2 Active
US6778266B2 Semiconductor wafer tilt monitoring on semiconductor fabrication equipment plate Physics 2 Expired
US9700950B2 Innovative multi-purpose dipping plate Performing Operations; Transporting 1 Active
US10056285B2 Semiconductor wafer device and manufacturing method thereof Emerging Cross-Sectional Technologies 1 Active
US9812346B2 Semiconductor wafer device and manufacturing method thereof Emerging Cross-Sectional Technologies 1 Active
US9893044B2 Wafer-level underfill and over-molding Electricity 1 Active
US10276531B2 Semiconductor device having a boundary structure, a package on package structure, and a method of making Electricity 1 Active
US10804234B2 Semiconductor device having a boundary structure, a package on package structure, and a method of making Electricity 0 Active
US11024618B2 Wafer-level underfill and over-molding Electricity 0 Active
US10504870B2 Mechanisms for forming bonding structures Electricity 0 Active
US10770331B2 Semiconductor wafer device and manufacturing method thereof Emerging Cross-Sectional Technologies 0 Active
US8927391B2 Package-on-package process for applying molding compound Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.