Method of grinding wafer stacks to provide uniform residual silicon thickness
US9082713B2 · kind B2 · utility
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2References
1Claims
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Assignee
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Key dates
| Filing date | Oct 27, 2014 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Oct 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/68381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of processing a device wafer in a wafer stack by chucking the wafer stack device side down and grinding the exposed side of the carrier wafer to parallel with the device wafer, and thereafter flipping the wafer stack and chucking the wafer stack carrier side down and grinding residual silicon from the device wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.