Non-volatile memory devices having reduced susceptibility to leakage of stored charges
US9082750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2014 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Mar 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0413
Abstract
Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.