Batch process for three-dimensional integration
US9082808B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2012 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Jul 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package is described which includes a first chip having a first surface and first sides having a first side-wall angle, and a second chip having a second surface and second sides having a second side-wall angle, which faces and is mechanically coupled to the first chip. The chip package is fabricated using a batch process, and the chips in the chip package were singulated from their respective wafers after the chip package is assembled. This is accomplished by etching the first and second side-wall angles and thinning the wafer thicknesses prior to assembling the chip package. For example, the first and/or the second side walls can be fabricated using wet etching or dry etching. Therefore, the first and/or the second side-wall angles may be other than vertical or approximately vertical.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.