Centralized management of high-contention cache lines in multi-processor computing environments
US9086974B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Sep 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Communications detected on a coherence interconnect may indicate that a cache line is associated with performance-reducing events. A high-contention cache line may be placed in sub-line coherency mode. Caches accessing the cache line are notified that the cache line is in sub-line coherency mode. The cache line may be associated with a counter in a centralized detection table that is incremented based on detecting the communications. The cache line may be a high-contention cache line when the counter satisfies a high-contention criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.