Method of forming a stacked low temperature transistor and related devices

US9087689B1 · kind B1 · utility

Assignee

• INOSO, LLC · US

Inventors

• Ziep Tran · Austin, US
• Kiyoshi Mori · Okazaki, JP
• Giang T. Dao · Milpitas, US
• Michael Edward Ramon · Houston, US

Key dates

• Filing date: Jul 11, 2014
• Grant date: Jul 21, 2015
• Expiry date: Jul 11, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/03

Abstract

A method of forming a stacked low temperature transistor and related devices. At least some of the illustrative embodiments are methods comprising forming at least one integrated circuit device on a front surface of a bulk semiconductor substrate, and depositing an inter-layer dielectric on the at least one integrated circuit device. A semiconductor layer may then be deposited on the inter-layer dielectric. In some embodiments, a transistor is formed within the semiconductor layer. In some examples, the transistor includes a gate structure formed over the semiconductor layer as well as source/drain regions formed within the semiconductor layer disposed adjacent to and on either side of the gate structure. A metal layer may then be deposited over the transistor, after which an annealing process is performed to induce a reaction between the source/drain regions and the metal layer.