Self aligned embedded gate carbon transistors
US9087811B2 · kind B2 · utility
3Cited by
6References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 16, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Oct 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Transistors with self-aligned source/drain regions a gate structure embedded in a substrate; self-aligned source and drain contacts embedded in the substrate around the gate structure; and a channel layer over the gate structure and self-aligned source and drain contacts. The source and drain contacts extend above the channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.