Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same
US9087870B2 · kind B2 · utility
15Cited by
2References
19Claims
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Key dates
| Filing date | May 29, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.