Invalid signal filtering method and shifter utilizing the method
US9088268B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 2012 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Dec 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shifter with invalid signal filtering mechanism, comprising: a first shifting stage, for receiving and capturing an input signal in a first clock cycle; and a second shifting stage, after the first shifting stage, for receiving the input signal from the first shifting stage, and for receiving a validity signal indicating whether the input signal is valid or invalid, before a second clock cycle next to the first clock cycle occurs; wherein the second shifting stage captures the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is valid, where the second shifting stage does not capture the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is invalid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.