Margin improvement for configurable local clock buffer
US9088279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Dec 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing margin circuit of a local clock buffer circuit may include an inverter logic gate having an inverter input and an inverter output, whereby the inverter input receives an input clock signal. A NAND logic gate includes a first NAND input coupled to the inverter output, a second NAND input, and a NAND output. The circuit also includes a logic device having a first logic device input that is coupled to the inverter output, a second logic device input that receives a mode selection signal, and a logic device output that couples to the second NAND input, whereby the NAND logic gate generates a first time delayed input clock signal and a second time delayed input clock signal, such that the first and the second time delayed input clock signal control a falling edge transition of a local clock signal derived from the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.