Circuit and method for testing jitter tolerance
US9088399B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2014 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Feb 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A transceiver circuit for self-test of jitter tolerance is disclosed. The transceiver circuit includes a transmitter circuit having an output coupled to an output terminal of the transceiver and a receiver circuit having in input coupled to an input terminal of the transceiver. The transceiver also includes a loopback path configured to provide a signal transmitted by the transmitter circuit to the input of the receiver circuit. The transceiver also includes a test control circuit that causes jitter to be introduced in the signal transmitted by the transmitter circuit when the test control circuit is operating in a self-test mode, but not when the test control circuit is operating in a non-test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.