Instrumentation of hardware assisted transactional memory system
US9092253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2009 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Nov 4, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.