Memory interface circuit
US9092305B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2012 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Mar 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a circuit for communicating with a memory is provided. The circuit includes a sorting circuit configured to receive a plurality of read and write transactions. The sorting circuit sorts the write transactions according to respective sizes of data to be written to the memory, and sorts the read transactions according to respective sizes of data to be read from the memory. A selection circuit is configured to select transactions for transmission to the memory, from the sorted read and write transactions, in an order that balances a quantity of data to be written to the memory over a first serial data link with a quantity of data to be read from the memory over a second serial data link. A transmitter is coupled to the selection circuit and is configured to transmit the selected transactions to the memory device on a serial data link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.