Memory management unit with pre-filling capability
US9092358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2012 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Nov 13, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/654
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.